Intel Starts Shipping High-NA EUV Silicon
Intel’s D1X fab in Oregon has moved its High‑NA EUV tool from installation (April 2024) to serial production, patterning critical layers of the Panther Lake Core Ultra Series 3 chips built on the 18A process node. The scanner’s 0.55 numerical aperture sharpens the smallest feature by about one‑third compared with legacy 0.33‑NA EUV, allowing a single exposure to replace two or three low‑NA steps. Intel reports yields on the High‑NA layers that match those of mature EUV tools, and the parts are already shipping to customers, meaning a $380 million capital expense is now amortized on real silicon rather than test wafers.
The move positions Intel ahead of its foundry rivals. While TSMC has postponed High‑NA adoption through its 2 nm and A16 generations, SK hynix, Samsung and IBM have all placed orders for similar machines, and ASML is scaling production to 12‑15 units per year, targeting about 20 by 2028. Intel’s strategy of dual‑qualifying 18A layers on both Low‑NA and High‑NA equipment gives it a learning runway before the next node (14A/10A) where High‑NA will become indispensable. The trade‑off is steep: a High‑NA exposure costs roughly 2.5 × a Low‑NA exposure and the optics halve the field size, forcing mask stitching. However, the production‑grade EXE:5200B model now reaches ~175 wafers per hour—a 60 % throughput gain—while larger 6‑by‑12‑inch masks mitigate the stitching penalty, addressing the primary economic concerns highlighted by SemiAnalysis and the imec roadmap.
Looking ahead, Intel’s early adoption could translate into a lead in performance‑critical laptop silicon if the cost curve improves and the higher dose requirements do not erode throughput. Risks include the still‑high per‑wafer cost, potential yield variability as more layers move to High‑NA, and the possibility that TSMC accelerates its own rollout, compressing Intel’s advantage. Watch for Intel’s first 14A/10A products that will rely exclusively on High‑NA, for ASML’s announced 2028 production rate, and for any pricing adjustments from foundry customers reacting to the higher exposure cost.
Key Takeaways
Intel’s Panther Lake CPUs are the first commercial products to incorporate layers printed on a High‑NA EUV scanner.
The $380 million, 165‑ton machine delivers a 0.55 NA, cutting required exposures by up to two‑thirds but halves the usable field, necessitating larger masks.
Intel’s dual‑qualification on 18A gives it a head start on future nodes where High‑NA will be mandatory, while TSMC remains hesitant through 2029.
The economics hinge on throughput gains (≈175 wafers/hr) and yield parity; any slowdown in these metrics could curb the anticipated cost advantage.
About the Source
This analysis is based on reporting by Hacker News. Here is a short excerpt for context:
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